The present invention relates in general to semiconductor memories and in particular to an in improved interface and pin-out for synchronous semiconductor memories.
To improve the speed of memory circuits such as dynamic random access memories (DRAMs), a new generation of memory circuits has been developed that operates in response to a system clock. The system clock enables the memory circuit to operate synchronously with the associated controller. Thus, every read and write operation is synchronized with one edge, usually the rising edge, of the system clock. Referring to FIG. 1, there is shown a simplified block diagram of a prior art system using a single clock synchronous memory device 100. A clock driver or generator 102 generates a clock signal CLK and supplies CLK to memory device 100. A controller 104 connects to both memory device 100 and clock driver 102. In existing systems, clock driver 102 is typically required to guarantee only the timing of the rising edge of the clock signal CLK which triggers the various operations of the system. There may be as much as 15% variation in the failing edge of CLK, resulting in a clock signal that does not have a 50% duty cycle. This is tolerable since all system activity is synchronized to the rising edge of CLK. FIG. 2 is a timing diagram illustrating a read operation of the prior art single clock memory device. As shown, both the read command and the data outputs occur at rising edges of CLK signal while the falling edge which exhibits variations in its timing is essentially ignored. Therefore, given for example a CLK signal with a 10 ns period, the 15% variation in the falling edge leaves only about a 3.5 ns window for data processing.
The synchronous operation of the memory has improved the speed and bandwidth of the memory circuit by allowing the use of circuit techniques such as pipelining. However, given current microprocessors that operate much faster than the associated DRAMs, there is always a demand for faster memory chips with greater bandwidth.